1. Field of the Invention
This invention relates generally to the execution of instructions by computer systems and more particularly to delaying indirect register offset resolution in a computer.
2. Description of the Background Art
Implementing an efficient and effective method for the utilization of registers in compilers to generate "good code" (code that is accurate, efficient, and fast) is a significant consideration of system designers and manufacturers. However, the techniques for register utilization in reduced instruction word compilers often produce cumbersome and slow object code.
Compilers are used to translate high-level languages, such as Pascal or C++, into executable object code. Typically, the compiler achieves this translation in a series of phases or passes through the code. First, the compiler translates the high-level language source code into intermediate code (usually, assembler code), which may take one or more passes through the code. The compiler then optimizes the intermediate code into assembler code. The optimization may be accomplished in one or more passes through the code. Finally, the compiler translates the output of the optimization phases into object code that is suitable for execution by the computer system.
In order to reduce the memory requirements for microprocessors, system designers and manufacturers are designing high-speed microprocessors for embedded applications with 16-bit instruction words rather than 32-bit instruction words. For example, the Hitachi-SH microprocessor is such a 16-bit instruction word microprocessor. With reduced instruction words, the offset value in indirect offset addressing is reduced, resulting in a reduced amount of contiguous memory addressable for a given instruction. Indirect offset (or indexed) addressing is an addressing mode incorporated in many microprocessor instruction sets.
In an indirect addressing mode instruction (for example, "mov.l@r4,r8"), the indirectly addressed register (r4) contains the address (effective address) within memory to be operated on. For example, if r4 contains 1024, then the instruction above would move the contents of memory address 1024 into register eight (r8). In an indirect offset (or indexed) addressing mode instruction, an offset value is first added to the contents of the indirectly addressed register to arrive at the effective address before the operation takes place. For example, for the instruction "mov.l@(8,r4),r8" (in which "@(8,r4)" is the indirect offset address reference), the offset value "8" is added to the value found in r4, resulting in the effective address. If r4 contains 1024, the effective address is 1032, and the contents of memory address 1032 is moved into r8.
Typically, indirect offset addressing is an efficient method for referencing fields within large data structures as the offset need only be manipulated to move through the fields. In 32-bit instruction word microprocessor systems, the offset field in the instruction word is usually adequate to access the entire range of addressable memory. However, in reduced instruction word systems, because of the reduced offset, the compiler must load a new value into the indirectly addressed register (r4) for the microprocessor to access the full range of addressable memory.
Typically, reduced instruction word compilers have overcome the problem of a reduced offset by the compiler generating address calculations for each indirect offset register reference during optimization. However, this approach reduces the efficiency of the reduced instruction word system. For example, a typical compiler would translate the out-of-range instruction "mov.l@(8,r4),r8" into three instructions: (1) "mov r4,r5", (2) "add #8,r5" and (3) "mov.l@r5,r8". The original instruction requires only one register access whereas the three resulting instructions now require three register accesses. Thus, a single instruction is replaced with three instructions, resulting in cumbersome and slow object code.
Thus, the foregoing problems present significant obstacles to effectively implementing an efficient method for using registers in compilers to generate good code.